The present invention relates to a semiconductor device and can be used appropriately for a semiconductor device having, e.g., a FINFET.
In recent years, in an LSI (Large Scale Integration) using silicon, the sizes of MISFETs (Metal Insulator Semiconductor Field Effect Transistors) as the components thereof, especially the gate lengths of gate electrodes have been increasingly reduced. The size reduction of MISFETs has been pursued in accordance with the scaling law. However, as the generations of devices have passed on, various problems have been encountered, and it has become difficult to simultaneously suppress a short-channel effect in a MISFET and ensure a current driving force therefor. Accordingly, research and development on devices with novel structures which may replace conventional planar (plane-type) MISFETs has been actively promoted.
A FINFET is one of the above-mentioned devices with novel structures and uses the side surfaces of a FIN (active region) as channels to have an improved current driving force.
On the other hand, as one of nonvolatile memories, there is a memory cell made of a split-gate cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film. The memory cell includes two MISFETs which are a control transistor having a control gate electrode and a memory transistor having a memory gate electrode. By applying a FIN structure also to these transistors, it is possible to improve the characteristics of the memory.
Japanese Unexamined Patent Publication No. 2006-41354 (Patent Document 1) discloses a technique in which, in a nonvolatile semiconductor device having a split-gate structure, a memory gate is formed over a protruding substrate and the side surfaces thereof are used as channels.
Japanese Unexamined Patent Publication No. 2006-54292 (Patent Document 2) discloses split-gate memory cells each having a selection transistor and a memory transistor and a technique which physically spaces the selection gate electrodes apart from each other over an isolation insulating film, forms an auxiliary pattern between the selection gates spaced apart from each other, and leaves sidewall electrodes between the auxiliary pattern and the selection gate electrodes. The sidewall electrodes are used to supply power to the memory gate electrodes.